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Uart Serial Communication Using Vhdl

IntroductionIn this chapter, UART communication is discussed for NIOS design. Values of Sin(x) is generated using NIOS and the data is received by computer using UART cable. Since, onchip memory is smaller for storing these values, therefore external memory i.e.

SDRAM is used. Further, the received data is stored in a file using ‘Tera Term’ software; finally live-plotting of data is performed using Python.In this chapter, we will learn following topics,. UART interface,. Receiving the data on computer using UART communication,. SDRAM interface,.

Saving data generated by NIOS desgin to a file using ‘Tera Term’,. Updating a existing QSys design and corresponding VHDL and NIOS design,. Live-plotting of data using Python. UART interfaceFirst, create a empty project with name ‘UartComm’ (see ). Next, open the QSys from Tools–Qsys.

Vhdl code for uart transmitter

Uart Receiver Vhdl

Add ‘Nios Processor’, ‘On-chip RAM (with 20k total-memory-size), ‘JTAG UART’ and ‘UART (RS-232 Serial Port)’ ( all with default settings). Note that, Baud rate for UART is set to ‘115200’ (see ), which will be used while getting the data on computer. Lastly, connect these items as shown in; save it as ‘UartQsys.qsys’ and finally generate the Qsys system and close the Qsys. Please see, if you have problem in generating the QSys system. NIOS designIn, we created the ‘BSP’ and ‘application’ file separately for NIOS design.

In this chapter, we will use the template provided with NIOS to create the design. For this, open the NIOS software and go to ‘Files–New–NIOS II Application and BSP from Template’.

Next, Select the ‘UARTQsys.sopcinfo’ file and ‘Hello World’ template and provide the desired name to project e.g. UARTcommapp, as shown in Fig, and click ‘next’. In this window, enter the desired name for BSP file in the ‘Project name’ column e.g. ‘UARTcommbsp’; and click on Finish. Communication through UARTTo received the data on computer, we need some software like Putty or Tera Term. In this tutorial, we are using ‘Tera Term software, which can be downloaded freely. Also, we need to change the UART communication settings; so that, we can get messages through UART interface (instead of JTAG-UART) as shown next.Right click on ‘UARTcommbsp’ and go to ‘NIOS II–BSP editor’; and select UART115200 for various communication as shown in; and finally click on generate and then click on exit.

Uart Serial Communication Using Vhdl

Now, all the ‘printf’ statements will be send to computer via UART port (instead of Jtag-uart). We can change it to JTAG-UART again, by changing UART115200 to JTAG-UART again.

Note that, when we modify the BSP using BSP-editor, then we need to generate the system again. 14.13 Assigning Pins to SDRAM and SwitchesNote that, there should be ‘-3 ns clock delay’ for SDRAM as compare to FPGA clock, therefore we need to add the clock with ‘-3 ns delay’. For this, double click on the Uarttop.bdf (anywhere in the file), and select ‘MegaWizard Plug-In Manager’. Then select ‘Create a new custom megafunction variation’ in the popped-up window and click next. Now, select ALTPLL from IO in Installed Plug-Ins option, as shown in, and click next. Then, follow the figures from to to add the ALTPLL to current design i.e.

Finally, connect the ports of this design as shown in. Note that, in these connections, output of ATLPLL design is connected to ‘DRAMCLK’, which is clock-port for DRAM. Lastly, compile and load the design on FPGA board. Updating NIOS designSince, we have udpated the QSys design, therefore the corresponding.sopcinfo file is also updated. Further, BSP files depends on the.sopcinfo file, therefore we need to update the BSP as well. For this, right click on ‘Uartcommbsp’ and go to ‘NIOS II–BSP Editor; and update the BSP as shown in and click on ‘generate’ and then click ‘exit’.

Note that, ‘enable’ options are unchecked now, because we are using External memory, which is quite bigger than onchip-memory, so we do not need ‘small’ size options. Live plotting the dataIn the previous section, we store the sine and cosine wave data on the ‘sineData.txt’ using UART communication. Now, our last task is to plot this data continuously, so that it look line animation. For this save the, in the location where ‘sineData.txt’ is saved. Now, open the command prompt and go to the location of python file.

Finally, type ‘python main.py’ and press enter. This will start plotting the waveform continuously based on the data received and stored on the ‘sineData.txt’ file.

Uart Serial Communication Using Vhdl Code

The corresponding plots are shown in. Import matplotlib.pyplot as plt import matplotlib.animation as animation fig = plt. Figure ax1 = fig. Addsubplot ( 2, 1, 1 ) ax2 = fig. Addsubplot ( 2, 1, 2 ) def animate ( i ): readData = open ( 'sineData.txt', 'r' ).

Read data = readData. Split ( ' n ' ) sinarray = cosarray = for d in data: if len ( d ) 1: sin, cos = d. Split ( ',' ) sinarray.

Uart Fifo Vhdl

Append ( sin ) cosarray. Append ( cos ) ax1. Clear ax1. Plot ( sinarray ) ax2. Clear ax2. Plot ( cosarray ) def main : ani = animation. FuncAnimation ( fig, animate ) plt.

Show if name 'main': main.